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digital-clock
- vhdl文件,实现数字钟,以及其顶层设计图-This package contains the VHDL file, can realize the digital clock, contains the top-level design
FPGA_exp2
- 调节数码管显示的文件,适用于CYCLONE II 开发板, 用VHDL语言编写,非常适合移植进数字钟中以实现调节时间的功能。 多模块设计简单明了。-Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regula
EDA实验程序
- VHDL语言编写简单EDA实验程序,如数字钟,,译码器,,动态扫描数码管(VHDL language, simple EDA experimental procedures)